Bonding Pad on a Back Side Illuminated Image Sensor

ABSTRACT

A bonding pad structure comprises an interconnect layer, an isolation layer over the interconnect layer, a conductive pad, and one or more non-conducting stress-releasing structures. The conductive pad comprises a planar portion over the isolation layer, and one or more bridging portions extending through at least the isolation layer and to the interconnect layer for establishing electric contact therewith, wherein there is a trench in the one or more bridging portions. The one or more non-conducting stress-releasing structures are disposed between the isolation layer and the conductive pad. The trench is surrounded by one of the one or more non-conducting stress-releasing structures from a top view.

PRIORITY

The present application is a divisional of U.S. application Ser. No.15/012,300 filed on Feb. 1, 2016, which is a divisional of U.S.application Ser. No. 13/763,355, entitled “A Bonding Pad on a Back SideIlluminated Image Sensor” filed Feb. 8, 2013, the entire disclosure ofeach is herein incorporated by reference in their entirety.

BACKGROUND

Semiconductor image sensors are used to sense radiation such as light.Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) andcharge-coupled device (CCD) sensors are widely used in variousapplications such as digital still camera or mobile phone cameraapplications. These devices utilize an array of pixels in a substrate,including photodiodes and transistors that can absorb radiationprojected toward the substrate and convert the sensed radiation intoelectrical signals. A back side illuminated (BSI) image sensor device isone type of image sensor devices. These BSI image sensor devices areoperable to detect light from its backside.

The conventional sensor, called the “front side illumination (FSI)”image sensor for these CMOS chips, is constructed in a fashion similarto the human eye, and has a lens at the front, layers of metal havingwiring in the middle, and photo detectors on a silicon substrate (whichabsorbs the light) at the back. These metal layers may not only deflectthe light on the sensor, they could also reflect it, reducing theincoming light captured by the photo detectors. By contrast, the backside illuminated sensor has the same elements as FSI, but orients thewiring behind the photo detectors layer by flipping the silicon waferduring manufacturing and then thinning its reverse side so that lightwill hit the silicon first, and the photo detectors layer withoutpassing through the wiring layer. This change can improve the chance ofan input photon being captured from about 60% to over 90%, and thesensitivity per unit area to deliver better low-light shots.

A BSI image sensor device typically has a device region of a wafer and abond pad region. One of the failure mechanisms known for the bond pad iscratering, which is a mechanical damage to the bonding pad. Crateringhappens when the bond pad is peeled off, by some upwardly pulling force,along with a chunk of silicon and in many cases part of active circuitunderneath the bond pad, thereby creating a ‘hole’ or ‘crater’ on thesilicon substrate. It causes a partial or total fracture of the siliconmaterial underneath the bond pad. Bonding time, force and power arecritical parameters when dealing with cratering.

Such cratering or bonding pad peeling not only degrades, but seriouslydamages BSI image sensor device performance. Therefore, it is desirableto provide a method of designing and manufacturing a bond pad structurein an image sensor device, such as BSI, such that any excess stressesthat might be potentially applied to the silicon substrate layer may beadequately released or redistributed to prevent the cratering or bondpad peel-off problem.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are understood from the followingdetailed description when read with the accompanying figures. It isemphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIG. 1 is a diagrammatic cross-sectional side view of a BSI image sensordevice fabricated according to an aspect of the present disclosure;

FIGS. 2A-2C are top cross-sectional, and side cross-sectional schematicviews, respectively, of the conventional bonding pad structure in thecurrent art for an image sensor device;

FIG. 3 is a flowchart of a method for fabricating a bonding padstructure for an image sensor device, such as the one illustrated inFIG. 1, according to an aspect of the present disclosure;

FIGS. 4A-4H are schematic diagrams for the steps performed in the methodillustrated in FIG. 3, in an aspect of the present disclosure; and

FIGS. 5A and 5B are top cross-sectional, and side cross-sectionalschematic views, respectively, of a bonding pad structure made in anaspect of the present disclosure.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof the invention. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Moreover,the formation of a first feature over or on a second feature in thedescription that follows may include embodiments in which the first andsecond features are formed in direct contact, and may also includeembodiments in which additional features may be formed interposing thefirst and second features, such that the first and second features maynot be in direct contact. Various features may be arbitrarily drawn indifferent scales for the sake of simplicity and clarity.

FIG. 1 is a diagrammatic cross-sectional side view of a BSI image sensordevice 100 fabricated according to an aspect of the present disclosure.The image sensor device 100 includes an array or grid of pixels forsensing and recording an intensity of electromagnetic radiation or wave(such as light) directed toward a back-side thereof. The image sensordevice 100 may include a charge-coupled device (CCD), complimentarymetal oxide semiconductor (CMOS) image sensor (CIS), an active-pixelsensor (APS), or a passive-pixel sensor. The image sensor device 100further includes additional circuitry and input/outputs that areprovided adjacent to the grid of pixels for providing an operationenvironment for the pixels and for supporting external communicationwith the pixels. It is understood that FIGS. 1, and 2-5 have beensimplified for a better understanding of the inventive concepts of thepresent disclosure and may not have been drawn to scale.

With reference to FIG. 1, the image sensor device 100 generallycomprises a radiation-sensing region 110, a periphery region 120, abonding pad region 130 (also referred to as an E-pad region), and ascribe line region 140. The dashed lines in FIG. 1 designate theapproximate boundaries between the regions 110, 120, 130, and 140. It isunderstood that these regions 110, 120, 130, and 140 extend verticallyabove and below the device substrate 102. The radiation-sensing region110, to be described more in detail herein below, includes siliconsubstrate that receives radiation and radiation-detection devices formedtherein. The periphery region 120 may include other devices 122 and 124that need to be kept optically dark. For example, the device 122 in anembodiment may be a digital device, such as an application-specificintegrated circuit (ASIC) device or a system-on-chip (SOC) device. Theother device 124 may be a reference pixel that is used to establish abaseline of an intensity of light for the image sensor device 100. Thebonding pad region 130 may include one or more conductive bonding padsor E-pads, through which electrical connections between the image sensordevice 100 and outside devices may be established. The structure andfabrication of the bonding pad region 130 according to aspects of thepresent disclosure may be described more in detail herein through FIGS.3-5. The scribe line region 140 may be the region that separates onesemiconductor die that includes the bonding pad region 130, theperiphery region 120, and the radiation-sensing region 110) from anadjacent semiconductor die (not illustrated). The scribe line region 140is cut in a later fabrication process to separate adjacent dies beforethe dies are packaged and sold as integrated circuit chips. The scribeline region 140 is cut in such a way that the semiconductor devices ineach die are not damaged.

Referring back to FIG. 1, the radiation-sensing region 110 includes adevice substrate 102. The device substrate 102 is a silicon substratedoped with a p-type dopant such as boron (for example a p-typesubstrate) or an n-type dopant such as phosphorous or arsenic (an n-typesubstrate). The substrate 102 may be comprised of a singlesemiconducting material such as bulk silicon or any other suitableelementary semiconducting materials, such as germanium in crystal; acompound semiconductor, such as silicon carbide, silicon germanium,gallium arsenic, gallium phosphide, indium phosphide, indium arsenide,and/or indium antimonide; or combinations thereof. The substrate 102 mayalso include an insulator layer on top of the semiconductor layer. Theinsulator layer comprises any suitable material, including siliconoxide, sapphire, other suitable insulating materials, and/orcombinations thereof. An exemplary insulator layer may be a buried oxidelayer (BOX). The insulator is formed by any suitable process, such asseparation by implantation of oxygen (SIMOX), oxidation, deposition,and/or other suitable process. Alternatively, the substrate 102 mayfurther include another semiconductor layer on top of an insulator layerto form a silicon-on-insulator (SOI) substrate, which can be fabricatedusing wafer bonding, and/or other suitable methods. The substrate 102may comprise any suitable crystallographic orientation (e.g., a (100),(110), (111), or (001) crystallographic orientation).

The substrate 102 has a front side 104 and a back side 106. The typicalthickness of the device substrate 102 may range between about 100microns (um) and 3000 um. In the device substrate 102, radiation-sensingregions 110 may be formed, which includes radiation-detection devices,pixels 112 and 114. The pixels 112 and 114 are operable to senseradiation, such as an incident light 115, that is projected toward theback side 106 of the device substrate 102. Each of the pixels 112 and114 may include a photodiode in one embodiment. In another embodiment,the pixels 112 and 114 may include pinned layer photodiodes, photogates,reset transistors, source follower transistors, and transfertransistors.

The pixels 112 and 114, though drawn schematically identically, may bevaried from one another to have different junction depths, thicknesses,widths, and so forth. Also, only two pixels are illustrated in FIG. 1for the sake of simplicity, but it is understood that any number ofradiation-detection devices may be implemented in the device substrate102. In one embodiment shown, the pixels 112 and 114 may be formed byperforming a suitable implantation process on the device substrate 102from the front side 104. The implantation process may include doping thedevice substrate 102 with a p-type dopant such as boron or an n-typedopant such as phosphorous or arsenic. In another embodiment, the pixels112 and 114 may also be formed by a diffusion process.

Continuing to refer to FIG. 1, the radiation-sensing region 110 of thedevice substrate 102 may further include isolation structures—forexample, isolation structures 116 and 118—that provide electrical andoptical isolation between the pixels 112 and 114. The isolationstructures 116 and 118 may include shallow trench isolation (STI)structures that are formed of a dielectric material such as siliconoxide or silicon nitride. The STI structures are formed by etchingopenings into the substrate 102 from the front side 104 and thereafterfilling the openings with the dielectric material. In other embodiments,the isolation structures 116 and 118 may include doped isolationfeatures, such as heavily doped n-type or p-type regions. It isunderstood that the isolation structures 116 and 118 are formed beforethe pixels 112 and 114. Again, only two isolation structures 116 and 118are illustrated in FIG. 1 for the sake of simplicity, but it isunderstood that any number of isolation structures may be implemented inthe device substrate 102 so that the radiation-sensing regions such aspixels 112 and 114 may be properly isolated.

Referring back to FIG. 1, the image sensor device 100 may further havean interconnect structure 150 formed over the front side 104 of thedevice substrate 102. The interconnect structure 150 may include aplurality of patterned dielectric layers and conductive layers thatprovide interconnections (e.g., wiring) between the various dopedfeatures, circuitry, and input/output of the image sensor device 100.The interconnect structure 150 may further include an interlayerdielectric (ILD) 156 and a multilayer interconnect (MLI) structure. TheMLI structure includes contacts, vias and metal lines. For the purposesof illustration, a plurality of conductive metal lines 152 andvias/contacts 154 are shown in FIG. 1. It should be understood that theconductive lines 152 and vias/contacts 154 illustrated are merelyexemplary, and the actual positioning and configuration of theconductive lines 152 and vias/contacts 154 may vary depending on designneeds.

Still referring to FIG. 1, the image sensor device 100 may furtherinclude a buffer layer 160 formed on the interconnect structure 150. Inthe present embodiment, the buffer layer 160 includes a dielectricmaterial such as silicon oxide. Alternatively, the buffer layer 160 mayoptionally include silicon nitride. The buffer layer 160 is formed byCVD, PVD, or other suitable techniques. The buffer layer 160 may beplanarized to form a smooth surface by a chemical mechanical polishing(CMP) process.

Thereafter, a carrier substrate 165 may be further bonded with thedevice substrate 102 through the buffer layer 160, so that processingthe back side 106 of the device substrate 102 can be performed. Thecarrier substrate 165 in the present embodiment is similar to thesubstrate 102 and includes a silicon material. Alternatively, thecarrier substrate 165 may include a glass substrate or another suitablematerial. The carrier substrate 165 may be bonded to the devicesubstrate 102 by molecular forces—a technique known as direct bonding oroptical fusion bonding—or by other bonding techniques known in the art,such as metal diffusion or anodic bonding.

The buffer layer 160 provides electrical isolation between the devicesubstrate 102 and the carrier substrate 165. The carrier substrate 165provides protection for the various features formed on the front side104 of the device substrate 102, such as the pixels 112 and 114. Thecarrier substrate 165 also provides mechanical strength and support forprocessing the back side 106 of the device substrate 102 as discussedbelow. After bonding, the device substrate 102 and the carrier substrate165 may optionally be annealed to enhance bonding strength.

Still referring to FIG. 1, a thinning process may be performed to thinthe device substrate 102 from the backside 106. The thinning process mayinclude a mechanical grinding process and a chemical thinning process. Asubstantial amount of substrate material may be first removed from thedevice substrate 102 during the mechanical grinding process. Afterwards,the chemical thinning process may apply an etching chemical to the backside 106 of the device substrate 102 to further thin the devicesubstrate 102 to a thickness desired. In one embodiment, the thicknessmay be less than 5 um, even down to 2-3 um. The thickness of the devicesubstrate 102 may be implemented depending on the type of applicationand design requirements of the image sensor device 100.

After thinning the substrate to a desired thickness, in order toconstruct a bonding pad structure in the bonding pad region 130, part ofthe substrate 102 in the bonding pad region 130 and the scribe lineregion 140 is further removed by an etching process, starting from theback side 106 of the substrate, until an interlayer dielectric layer(ILD) 156 on the interconnect structure 100 is exposed. FIG. 1 shows thebonding pad region 130 after the substrate 102 has been already removedby a proper etching process. After removing a portion of the substrate102 as desired. After then, an oxide layer 170 is formed over the backside 106 of the device substrate 102, and also over the exposed surfaceof the ILD layer 156 in the bonding pad region 130. Thereafter, aportion of the bonding pad region 130 is etched to expose a portion ofthe top-most conductive line in the interconnect structure 150. Abonding pad will be formed on the exposed conductive line. Then, aconductive layer 180 is formed over the oxide layer 170 from thebackside 106 and over the conductive line in the bonding pad region 130.A portion of the conductive layer 180 comes into physical contact withthe top-most conductive line in the interconnect structure 100 throughvias. This portion of the conductive layer will be patterned into abonding pad later. Detailed description of the etching process, formingthe oxide layer 170, and forming the conductive layer 180 will beprovided herein below when describing the process of constructing abonding pad structure in embodiments of the present disclosure.

Thereafter, though not illustrated in FIG. 1, an additional processingmay be performed to complete the fabrication of the image sensor device100. For example, a passivation layer may be formed around the imagesensor device for protection (for example against dust or humidity).Color filters may be formed within the radiation-sensing region 110. Thecolor filters may be positioned such that the incoming light is directedthereon and therethrough. The color filters may include a dye-based (orpigment based) polymer or resin for filtering a specific wavelength bandof the incoming light, which corresponds to a color spectrum (e.g., red,green, and blue). Thereafter, micro-lenses are formed over the colorfilters for directing and focusing the incoming light toward specificradiation-sensing regions in the device substrate 102, such as pixels112 and 114. The micro-lenses may be positioned in various arrangementsand have various shapes depending on a refractive index of material usedfor the micro-lens and distance from a sensor surface. It is alsounderstood that the device substrate 102 may also undergo an optionallaser annealing process before the forming of the color filters or themicro-lenses.

In the bonding pad region 130 of the image sensor device 100, a bondingpad structure is formed. FIGS. 2A-2B illustrate the bonding padstructures used in the current art that has a bonding pad peeling-offproblem, and in comparison, FIGS. 3-4H illustrate a method forfabricating a bonding pad structure in aspects of the present disclosurethat solves such a problem and FIGS. 5A-5B illustrate so fabricatedstructure.

FIGS. 2A and 2B show top cross-sectional, and side cross-sectionalschematic views, respectively, of the conventional bonding pad structure200 in the current art for an image sensor device. The conventionalbonding pad structure 200 includes a multilayer interconnect layer 202,an interlayer dielectric (ILD) layer 204, a dielectric layer such as ashallow trench isolation (STI) 206, and a conductive bonding padcomprising a horizontal planar portion 208 a disposed upon the STI layer206 and one or more vertical portions (vias) 208 b that extendsperpendicularly downward from the horizontal portion 208 a to reach themultilayer interconnect layer 202 through the STI layer 206 and ILDlayer 204. The conductive bonding pad 208 a and 208 b is typically madeof aluminum (Al), copper (Cu), or their combination (AlCu).

Upon the planar portion of the conductive pad 208 a, a process of wirebonding is performed for providing electrical connection between thechip (image sensor device) and the external leads of the semiconductordevice by using very fine bonding wires. The wire used in wire bondingis usually made either of gold (Au) or aluminum (Al), although Cu wirebonding is starting to gain a foothold in the semiconductormanufacturing industry. One common wire bonding process is a gold orcopper ball bonding. During this process, a copper, aluminum, or goldball is first formed by melting the end of a wire, which is held by abonding machine known as a capillary, through electronic flame-off(EFO). This free-air ball typically has a diameter ranging from 1.5 to2.5 times the wire diameter. The free-air ball is then brought intocontact with the bonding pad. Adequate amounts of pressure, heat, andultrasonic forces are then applied to the ball for a specific amount oftime, forming the initial metallurgical weld between the ball and thebonding pad as well as deforming the ball bond itself into its finalshape.

The bonding between the bonding pad and the ball must be strong andstable enough to withstand any external disturbance or force. If thebond fails, it will cause a ball lifting, a detachment of the ball fromthe bonding pad, or a cratering, caused by a peeling of the bonding pad.One of several available time-zero tests for wire bond strength andquality is the Wire Pull Testing (WPT), or bond pull testing, whichconsists of applying a perpendicularly upward force under the wire to betested via a pull hook, effectively pulling the wire away from the die,using a special equipment commonly referred to as a wire pull tester (orbond pull tester), and measure the force, in grams-force, at which thewire or the bond fails. This breaking force is usually expressed.

This conventional bonding pad structure, illustrated in FIGS. 2A and 2B,has, particularly, a problem of bonding pad peeling-off or a crateringunder such a wire pull testing. FIG. 2C schematically illustrates such aproblem. As pull force is applied to the ball 210 and the ponding pad208 a and 208 b by, for instance, pulling the wire 212 upward, the pad208 a and 208 b will be peeled off from the STI layer 206 atsufficiently large force. But when the ponding pad 208 a and 208 b ispeeled, it comes off not only by itself, but also together with a chunk220 of silicon or part of metal conducting lines, which become dislodgedfrom the multilayer interconnect layer 202 and attached to the verticalportions of the bonding pad 208 b, leaving behind craters or holes 225in the multilayer interconnect layer 202. The common causes of crateringmay be due to excessive probing or overbonding, i.e., the situationwherein the bonding tool has transmitted excessive stresses to the bondpad during wire bonding. The excessive pull force or stress may pass thehorizontal ponding pad 208 a, be transferred through the verticalportion (vias) 208 b, and become centralized on the end of the verticalportions of the bonding pad 208 b to peel off the inner structure of themultilayer interconnect layer 202.

Such a cratering or peeling-off problem may happen not only to a bondpad structure that uses a bond ball process described above, but also toa structure that uses aluminum wedge wire bonding. In the wedge bondingprocess, a clamped aluminum wire is brought in contact with the aluminumbond pad. Ultrasonic energy is then applied to the wire for a specificduration while being held down by a specific amount of force, forming awedge bond between the wire and the bond pad.

Therefore, it is desired to provide a structure for bonding pad that isdesigned to spread out the stress so that it may not be focused on thebonding pad only to cause to peeling-off problem that contaminates ordestroys important electric connections contained in a multilayerinterconnect layer.

FIG. 3 is a flowchart of a method 300 for fabricating a bonding padstructure for an image sensor device, such as a back-side illuminated(BSI) image sensor, according to an aspect of the present disclosure. Indescribing method 300 herein, FIGS. 4A-4H are referred to, which showschematically the steps performed in the method 300 in an aspect of thepresent disclosure. The image sensor device, for which the method 300 ispracticed, comprises a radiation-sensor region having a substrate and aradiation detection device formed in it; and a bonding pad region havinga stack of an interconnect layer and an interlayer dielectric layer thatare extending from the radiation-sensor region into the bonding padregion as schematically shown in FIG. 1.

The method 300 begins with a step 302 of exposing a portion of theinterlayer dielectric (ILD) layer in the bond pad region of an imagingdevice for constructing the bonding pad structure thereupon. Asillustrated in FIG. 1, the image sensor device has an interconnectstructure formed over a front side the device substrate, which may beextending all the way across the radiation-sensor region as well as thebonding pad region. The interconnect structure may includemulti-interconnect layers and an interlayer dielectric (ILD) layerformed upon the multi-interconnect layers. FIG. 4A shows the schematicside cross-sectional view of the interconnect structure 400 in the bondpad region, comprising multi-interconnect layers 402 and an interlayerdielectric (ILD) layer 404. The interlayer dielectric (ILD) layer 404 isshown to be exposed at the step 302 by having removing a substrate thathad been above the interlayer dielectric (ILD) layer 404 by an etchingprocess.

The multi-interconnect layers 402 may have patterned dielectric layersand conductive interconnects, such as contacts, vias and metal lines,that provide interconnections between the various doped features,circuitry, and input/output of the image sensor device. Theinterconnects are made of conductive materials such as aluminum,aluminum/silicon/copper alloy, titanium, titanium nitride, tungsten,polysilicon, metal silicide, or combinations thereof, being referred toas aluminum interconnects. Aluminum interconnects may be formed by aprocess including physical vapor deposition (PVD) (or sputtering),chemical vapor deposition (CVD), atomic layer deposition (ALD), orcombinations thereof. Other manufacturing techniques to form thealuminum interconnect may include photolithography processing andetching to pattern the conductive materials for vertical connection (forexample, vias/contacts) and horizontal connection (for example,conductive metal lines). Alternatively, a copper multilayer interconnectmay be used to form the metal patterns. The copper interconnect mayinclude copper, copper alloy, titanium, titanium nitride, tantalum,tantalum nitride, tungsten, polysilicon, metal silicide, or combinationsthereof. The copper interconnect may be formed by a technique includingCVD, sputtering, plating, or other suitable processes.

The interlayer dielectric (ILD) layer 404 is formed between theinterconnects and upon the interconnect layers for electric isolation. Adielectric material is deposited to fill the spaces betweeninterconnects and over them to form the ILD layer. In one embodiment,the dielectric material may be the typical undoped and doped silicondioxide (SiO2), silicon oxynitride (SiON), and silicon nitride (Si3N4),or other high-k dielectric material such as a hafnium oxide (HfO₂),HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide,hafnium dioxide-alumina (HfO₂—Al₂O₃) alloy, titanium nitride (TiN). Inanother embodiment, the dielectric material may be low k (dielectricconstant) material, having k value less than 3, such as fluorinatedsilica glass, hydrogen silsesquioxane, carbon doped silicon oxide,amorphous fluorinated carbon, Parylene, B-stage polymers, BCB(bis-benzocyclobutenes), PTFE (Teflon), SiLK (Dow Chemical, Midland,Mich.), SiOC (silicon oxycarbide) polymers, polyimides/Fluorinated,Poly(arylene ether) PAE. In still another embodiment, the dielectricmaterial may be an ultra-low k dielectric material including a porousversion of an existing dielectric material, such as Porous MSQ, PorousPAE, Porous SiLK, or Porous SiO₂. After the deposition, the upperportions of deposited interlayer dielectric layer may be removed and/orflattened by, in an embodiment, a Chemical MechanicalPolishing/Planarization (“CMP”) so that it may be attached to the frontside of the substrate of the image sensor device.

As mentioned above, exposing the ILD layer 404 for constructing thebonding pad structure in the bond pad region at step 302 involvesremoving the portion of the substrate that was initially extending inthe bod pad region beyond the radiation sensor region of the device,starting from the back side of the substrate, by an etching processuntil the interlayer dielectric layer lying under the front side of thesubstrate becomes exposed. When etching the substrate, any known etchingprocesses may be used, such as wet etching, dry etching, or plasmaetching, but when an anisotropic etching is desired, a plasma etchingmay be used. In one embodiment, etching the polymer may use a mixture ofprocess gases. For instance, oxygen and tetrafluoromethane (CF4), whenmixed together for use in plasma etching, create the oxyfluoride ion(OF—). The oxyfluoride ion is a powerful etching agent for polymericsubstances. This ion is particularly adept at cutting the carbon-carbonmolecular bonds in the polymer backbone and removing the moleculequickly. The etchants that may be used for polymer etching may include,but are not limited to, wet etchants such as potassium hydroxide (KOH),ethylene diamine and pyrocatechol (EDP), or Tetramethylammoniumhydroxide (TMAH), or plasma etchants such as Cl₂, CCl₄, SiCl₂, BCl₃,CCl₂F₂, CF₄, SF₆, or NF₃.

Referring back to FIG. 3, now at step 304, an isolation layer is formedon the exposed portion of the interlayer dielectric layer. FIG. 4B showsthe isolation layer 406 formed upon the interlayer dielectric layer 404,exposed in the previous step of 302. The isolation layer 406 may beformed by utilizing isolation technology, such as local oxidation ofsilicon (LOCOS) or shallow trench isolation (STI), wherein a dielectricmaterial may be deposited by spin-on coating or spin-on dielectric (SOD)process, CVD, or any other suitable deposition processes upon theinterlayer dielectric layer 404. After the deposition, the upperportions of deposited dielectric layer may be removed by, in anembodiment, a Chemical Mechanical Polishing/Planarization (“CMP”). Thedielectric material used for the isolation layer 406 may be the typicalundoped and doped silicon dioxide (SiO₂), silicon oxynitride (SiON),silicon nitride (Si₃N₄), high-density plasma (HDP) oxides, TEOS oxides,high-k dielectric material such as a hafnium oxide (HfO₂), HfSiO,HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafniumdioxide-alumina (HfO₂—Al₂O₃) alloy, titanium nitride (TiN), or any othersuitable materials, or combinations thereof. In some embodiments, theisolation layer 406 may have a multi-layer structure such as a thermaloxide liner layer filled with silicon nitride or silicon oxide.

It is also understood that a bottom anti-reflective coating (BARC) layermay be further formed over the isolation layer 406, and an additionaloxide layer may be formed over the BARC layer. However, for reasons ofsimplicity, the BARC layer and the additional oxide layer are notillustrated herein.

Referring back to FIG. 3, at step 306, a plurality of non-conductingstress-releasing structures is formed on the isolation layer by suitablemultiple processes as schematically described in FIGS. 4C-4G. Suchprocesses may include deposition, photolithography patterning, andetching processes. The photolithography patterning processes may includephotoresist coating (e.g., spin-on coating), soft baking, mask aligning,exposure, post-exposure baking, developing the photoresist, rinsing,drying (e.g., hard baking), other suitable processes, and/orcombinations thereof. Alternatively, the photolithography exposingprocess may be implemented or replaced by other proper methods such asmask-less photolithography, electron-beam writing, and ion-beam writing.

More particularly, a photoresist (“PR”) layer 408 is coated upon theisolation layer 406 for patterning as shown in FIG. 4C. The photoresistmay be any suitable material used in the art, such as Poly (methylmethacrylate) (PMMA), Poly (methyl glutarimide) (PMGI), Phenolformaldehyde resin (DNQ/Novolac), SU-8, and may be either positive ornegative photoresist. These materials are all applied as a liquid and,generally, spin-coated to ensure uniformity of thickness. Afterprebaking, the photoresist layer is exposed to an ultraviolet (UV), deepultraviolet (DUV) or electron beam through a pattern via a photomask.The exposure to light causes a chemical change that allows some of thephotoresist to be removed by a special solution, called “developer” byanalogy with photographic developer. For positive photoresist, the mostcommon type, the exposed part becomes soluble in the developer. Aftergoing through a post-exposure baking process, the remaining (unexposed)parts form a mask that resists etching. FIG. 4(b) shows such photoresistmasks 408 after the exposure, developing, and post-exposure bakingprocess.

Next, a dielectric material is deposited, as shown in FIG. 4D, upon thephotoresist masks 408 and the isolation layer 406 to form a dielectriclayer 410, which will be shaped into the plurality of non-conductingstress-releasing structures later. The dielectric material may bedeposited by any suitable deposition processes including spin-on coatingor spin-on dielectric (SOD) process, CVD, or PVD. The dielectricmaterial used for stress-releasing structures may be the same materialas the shallow trench isolation (STI) layer such as the typical undopedand doped silicon dioxide (SiO₂), silicon oxynitride (SiON), siliconnitride (Si₃N₄), silicon carbonate (SiC), high-density plasma (HDP)oxides, TEOS oxides, high-k dielectric material such as a hafnium oxide(HfO₂), HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminumoxide, hafnium dioxide-alumina (HfO₂—Al₂O₃) alloy, titanium nitride(TiN), or any other suitable materials, or combinations thereof. Whiledepositing the dielectric material, the thickness of the layer 410 maybe controlled to have a suitable value to provide sufficient structuraland mechanical strength and stability when it is subsequently shapedinto the non-conducting stress-releasing structures.

After deposition of the dielectric layer 410, an etching is performed topartially remove the portions of the dielectric layer 410 that are rightabove the photoresist masks 408 and exposed portions of the isolationlayer 406, leaving only portions abutting two opposing sides of each ofthe photoresist masks 408 as shown in FIG. 4E. These remaining portionsform the plurality of non-conducting stress-releasing structures 410. Inone embodiment, for defining sharp edges and obtaining controlled widthof non-conducting stress-releasing structures 410, an anisotropicetching, such as the plasma or dry etching process, may be used. Theetchants may be any one that is known in the art such as Cl₂, CCl₄,SiCl₂, BCl₃, CCl₂F₂, CF₄, SF₆, or NF₃. In one embodiment, thesenon-conducting stress-releasing structures 410 generally have aconfiguration of an elongated rod or strip with a rectangular or squarecross section as shown in FIG. 4D. In another embodiment, they may haveany other geometrical or polygonal shapes.

Once the plurality of non-conducting stress-releasing structures 410 isformed by the partial etching, the exposed portions of the isolationlayer 406 and the interlayer dielectric layer 404 below are furtherremoved by another etching process, to define a plurality of trenches420 as shown in FIG. 4F. The etching process stops at the multilayerinterconnect structure 402. If necessary, an etch stop layer (notillustrated) may be further used. The etching process used here mayeither wet etching or dry etching.

After the etching process, the photoresist masks 408, which are nolonger needed, are removed by a process called the ashing. This usuallyrequires a liquid “resist stripper”, which chemically alters the resistso that it no longer adheres to the isolation layer 406. Alternatively,the photoresist masks 408 may be removed by a plasma containing oxygen,which oxidizes it. FIG. 4G shows the remaining portions of the structureafter the removal of the photoresist masks 408, which include theplurality of non-conducting stress-releasing structures 410.

Referring back to FIG. 3, lastly at step 308, a conductive pad is formedby depositing conductive material over the isolation layer 406, theplurality of non-conducting stress-releasing structures 410, and intothe plurality of trenches 420 to form a conductive pad, comprising twoportions, 430 and 440 as illustrated in FIG. 4H. The portions 440 of theconductive pad, partially filling the plurality of trenches 420, comedirectly into physical contact with the top-most conductive linesembedded in the multilayer interconnect structure 402. These verticalportions 440 of the conductive pad, the bridging portion, adjoin theplanar portion 430 of the conductive pad generally perpendicularly,extend through the isolation layers 406 and the interlayer dielectriclayer 404, and reach all the way down to the multilayer interconnectstructure 402 to establish electric contact therewith. The horizontalplanar portion 430 forms the bonding pad, to which bonding balls areattached by those processes, described with FIGS. 2A and 2B to establishelectrical connections between the image sensor device and externaldevices. In an embodiment, the conductive material may be a metal or ametal alloy material, for example aluminum (Al) or an aluminum copperalloy (AlCu).

In an embodiment, the conductive material may be deposited upon theradiation-sensor zone and other zones as well, and the planar portion ofthe conductive layer 430 may be extended to those regions. In that casean etching process may be performed to remove the portion of theconductive layer covering the radiation-sensor zone so that radiationthat is supposed to be detected by radiation detecting devices in thatzone will not be obstructed by the conductive layer (likely opaque).

FIGS. 5A and 5B show top cross-sectional, and side cross-sectionalschematic views, respectively, of a bonding pad structure 500 designedand manufactured by a method describe in FIGS. 3 and 4A-4H in anembodiment of the present disclosure. The bonding pad structure 500comprises a multilayer interconnect layer 502, an interlayer dielectric(ILD) layer 504, an isolation dielectric layer such as a shallow trenchisolation (STI) 506, a plurality of stress-releasing structures 510, anda conductive bonding pad, which comprises a horizontal planar portion530 disposed upon the STI layer 506 and one or more vertical portions(vias) 540 that extends perpendicularly downward from the horizontalportion 530 to reach the multilayer interconnect layer 502 through theSTI layer 506 and ILD layer 504. On the horizontal planar portion 530 ofthe conductive pad, conducting balls 550, which are made of copper,aluminum, or gold, are bonded for electric connection of the imagesensor device to external devices thereby. Each conducting ball 550 maybe positioned in the middle of two neighboring stress-releasingstructures 510 as shown in FIGS. 5A and 5B for better stress-releasingeffect.

The plurality of non-conducting stress-releasing structures 510 islocated between the conductive pad, the horizontal planar portion 530,and the isolation dielectric layer 506. It structurally adjoins theplanar and bridging portions 530 and 540 of the conductive layertogether as shown in FIG. 5B. With such a structure, any potentialpulling stress applied on the bonding pad structure would not beconcentrated on the horizontal and vertical portions 530 and 540 of theconductive pad, as distinguished from the conventional bonding padstructure illustrated in FIGS. 2A and 2B, but would be dispersed intothe plurality of the stress-releasing structures 510 as well. Then, thetotal stress applied to the conductive pad 530 and 540 would be reduced,and the bonding pad peeling-off or cratering problem describedhereinbefore for the conventional bonding pad structure would beprevented.

In one embodiment, the stress-releasing structures 510 may have a shapeof a rectangular wall with a rectangular side cross-section, erectedaround the trenches 520, as illustrated in FIGS. 5A and 5B. But inanother embodiment, they could take other shapes having differentgeometrical cross-sections such as polygons, a circle, or an ellipse.

The foregoing has outlined features of several embodiments so that thoseskilled in the art may better understand the detailed description thatfollows. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method of fabricating a bonding pad,comprising: forming an isolation layer over an interconnect layer;forming non-conducting stress-releasing structures over the isolationlayer, wherein the non-conducting stress-releasing structures each havea configuration of a surrounding wall from a top view; and forming aconductive pad comprising a planar portion overlying the isolationlayer, and one or more bridging portions extending through thesurrounding wall of the non-conducting stress-releasing structures, andthrough at least the isolation layer, and to the interconnect layer forestablishing electric contact therewith.
 2. The method of claim 1,wherein the device is a back side illuminated (BSI) image sensor.
 3. Themethod of claim 1, further comprising: bonding a conductive ball withthe planar portion of the conductive pad.
 4. The method of claim 1,wherein the forming of the non-conducting stress-releasing structuresincludes: depositing an oxide material to form an oxide layer, andpartially etching the oxide layer.
 5. The method of claim 1, wherein theforming of the conductive pad includes: etching at least the isolationlayer to form one or more trenches reaching down to the interconnectlayer; and depositing a conductive material over the isolation layer,over the non-conducting stress-releasing structures, and into the one ormore trenches.
 6. The method of claim 1, wherein the device comprises aninterlayer dielectric layer over the interconnect layer in the bondingpad region, and wherein the isolation layer is formed over theinterlayer dielectric layer.
 7. The method of claim 6, wherein theinterconnect layer includes spaces between interconnects and theinterlayer dielectric layer fills in the spaces.
 8. A method of forminga bonding pad structure, comprising: receiving a device having aninterconnect layer; forming an isolation layer over the interconnectlayer; depositing a dielectric layer over the isolation layer; removinga portion of the dielectric layer to form a structure over the isolationlayer and exposing a portion of the dielectric layer; and forming aconductive pad over the dielectric layer including over the exposedportion of the dielectric layer.
 9. The method of claim 8, furthercomprising, before forming the conductive pad, forming a trench in theisolation layer and the interconnect layer; and wherein the forming ofthe conductive pad includes forming the conductive pad in the trench ona sidewall of the isolation layer and a sidewall of the interconnectlayer.
 10. The method of claim 9, wherein the conductive pad is furtherformed on an exposed top surface of the interconnect layer.
 11. Themethod of claim 8, further comprising: before forming the isolationlayer, forming an interlayer dielectric layer over the interconnectlayer.
 12. The method of claim 8, wherein the conductive pad includes ahorizontal portion and a vertical portion.
 13. The method of claim 12,further comprising: bonding a conductive ball with the horizontalportion of the conductive pad.
 14. The method of claim 8, wherein thedielectric layer includes an oxide material.
 15. A method, comprising:forming an isolation layer over a backside of a semiconductor device;forming a dielectric layer overt the isolation layer; removing a portionof the dielectric layer to form a stress-releasing structure andexposing a portion of the isolation layer; and forming a conductivelayer over the stress-releasing structure including over the exposedportion of the isolation layer.
 16. The method of claim 15, furthercomprising: bonding a conductive ball with the conductive layer.
 17. Themethod of claim 16, further comprising: wherein the stress-releasingstructure includes a first portion and an adjacent second portion, andforming a trench in the isolation layer between the first portion of thestress-releasing structure and the second portion of thestress-releasing structure.
 18. The method of claim 17, furthercomprising: before forming the isolation layer, forming an interlayerdielectric layer over the backside of the semiconductor device; andforming the isolation layer over the interlayer dielectric layer. 19.The method of claim 18, wherein the forming of the trench in theisolation layer between the first portion and the second portionincludes forming the trench in the interlayer dielectric layer.
 20. Themethod of claim 19, wherein the forming of the conductive layer over thestress-releasing structure including over the exposed portion of theisolation layer includes forming the conductive layer in the trench.